The SN54 / 74LS48 is a BCD to 7-Segment Decoder consisting of NAND gates, input buffers and seven AND-OR-INVERT gates. Seven NAND gates and one driver are connected in pairs to make BCD data and its complement available  to  the  seven  decoding  AND-OR-INVERT  gates.  The  remaining NAND gate and three input buffers provide lamp test, blanking input/ripple-blanking input for the LS48.

The circuit accepts 4-bit binary-coded-decimal (BCD) and, depending on the state of the auxiliary inputs, decodes this data to drive other components. The relative positive logic output levels, as well as conditions required at the auxiliary inputs, are shown in the truth tables.

The  LS48  circuit  incorporates  automatic  leading  and/ or  trailing  edge zero-blanking control (RBI and RBO). Lamp Test (LT) may be activated anytime  when  the  BI/ RBO  node  is  HIGH.  Both  devices  contain  an  overriding blanking input (BI) which can be used to control the lamp intensity by varying the frequency and duty cycle of the BI input signal or to inhibit the outputs.

•Lamp Intensity Modulation Capability (BI/RBO)

•Internal Pull-Ups Eliminate Need for External Resistors

•Input Clamp Diodes Eliminate High-Speed Termination Effects